This invention generally relates to electronic memories, and more particularly, the invention relates to a technique and apparatus for performing write operations to a phase change material memory device.
A phase change material may be used to store the memory state for a memory cell of a semiconductor memory device. In this manner, phase change materials that are used in phase change material memory devices may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure. Generally any phase change material may be utilized to exhibit these two states. However, as an example, thin-film chalcogenide alloy materials may be particularly suitable.
The phase change may be induced reversibly. Therefore, the phase change material may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter, or vice versa, in response to temperature changes. In effect, when the phase change material is used in a memory cell, the memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states. The phase change may be induced by resistive heating that is caused by a current that flows through the material.
The memory cell of a phase change memory device is not limited to just two memory states (i.e., a xe2x80x9c1xe2x80x9d state and a xe2x80x9c0xe2x80x9d state), but instead the memory cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance determined states may be possible, allowing the storage of multiple bits of data in a single memory cell.
A variety of phase change alloys are known. Generally, chalcogenide alloys contain one or more elements from Column VI of the periodic table. One particularly suitable group of alloys is the GeSbTe alloys.
A potential difficulty with the use of a phase change material as a memory storage device is that the time needed to change from the crystalline state to the amorphous state may be significantly shorter than the time needed to change from the amorphous state to the crystalline state. In this manner, FIG. 1 depicts temperature profiles that cause a particular phase change material to change states. In particular, FIG. 1 depicts a crystallizing set pulse 20 that generally extends from about time T0 to time T2 to place the phase change material in the crystalline state. As shown, the set pulse 20 represents a momentary rise in the temperature of the phase change material. The set pulse 20 is to be contrasted to the reset pulse 10, a pulse that is also associated with a higher temperature of the phase change material but has a significantly shorter duration, as the reset pulse 10 extends from about time T0 to T1. Thus, the reset pulse 10 may be used to transform a phase change material-based memory cell from the crystalline state to the amorphous state, or xe2x80x9cresetxe2x80x9d the state of the memory cell to xe2x80x9c0.xe2x80x9d In contrast, the set pulse 20 may be used to set the state of the memory cell to xe2x80x9c1.xe2x80x9d
Due to the discrepancy in the time needed to set the phase change material-based memory cell versus the time needed to reset the cell, the write set cycle time (i.e., the time allocated to force the state of the cell to indicate a set bit, or a xe2x80x9c1xe2x80x9d) maybe ten to two hundred times longer than the write reset cycle time (i.e., the time allocated to force the state of the cell to indicate a reset bit, or a xe2x80x9c0xe2x80x9d).
A conventional approach for a memory device that exhibits such a discrepancy in time between different types of write cycles is to set the time allocated for a given write cycle to the time needed to perform the slowest possible write cycle. Thus, the slowest write cycle may effectively establish the write cycle speed of the memory device.
A conventional way to accommodate a slow memory device is to either use a high speed static random access memory (SRAM) cache or shift registers to buffer a high data rate burst. Alternatively, several slow speed memories may be mounted in parallel such that alternative pieces of data may be put into the data latch of the first memory, the next piece of data stored in the latch of the second memory, etc. However, a potential difficulty with these approaches is that a large number of memory chips may be required, and thus, there is a greater associated cost per bit.
Thus, there is a continuing need for a technique and/or arrangement to address one or more of the problems that are stated above.